Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
Pin Description
PIN
NAME
MAX8513
MAX8514
FUNCTION
Power-Fail Input. Connect PFI to an external resistive-divider between IN, PFI, and GND.
PFI
1
1
PFI senses V IN to detect voltage failure. Trip falling threshold at this input is 1.22V, with
20mV of hysteresis.
PFO
DH
LX
BST
DL
PVL
PGND
2
3
4
5
6
7
8
2
3
4
5
6
7
8
Power-Fail Output. Open-drain output that goes low if V PFI < 1.22V.
OUT1 High-Side Gate-Drive Output. DH drives the high-side N-channel MOSFET (Q1 in the
Typical Applications Circuits ). DH is a floating driver output that swings from LX to BST.
OUT1 High-Side Driver Return Path. The high-side FET driver uses BST and LX for its
respective high and low-side supplies.
OUT1 Boost Capacitor Connection for High-Side Gate Drive. Connect a 0.1μF ceramic
capacitor from BST to LX with a less than 5mm trace length.
OUT1 Low-Side Gate-Drive Output. DL drives the low-side N-channel MOSFET (Q2 in the
Typical Applications Circuits ). DL swings from 0 to V PVL .
OUT1 Gate-Drive Supply Bypass Connection. Connect PVL to VL through a 10 ? resistor
(R15), and bypass PVL to PGND with a minimum 1μF capacitor (C1).
Power-Ground Connection and Low-Side Supply for Dl Driver
Internal +5V Linear-Regulator Bypass Pin. Bypass VL to GND with a minimum 2.2μF
VL
9
9
ceramic capacitor (C10) and 5mm or less of trace length. VL should be connected to IN
when V IN < 5.5V.
COMP1
FB1
10
11
10
11
OUT1 Compensation Node. See the OUT1 Compensation section.
OUT1 Feedback Input. Connect a resistive-divider (R1, R2) from OUT1 to FB1 to GND to
regulate FB1 at 1.25V.
Oscillator Frequency-Set Input. A resistor from FREQ to GND sets the oscillator frequency
FREQ
12
12
from 300kHz to 1.4MHz (f = 15MHz x k ? / R FREQ ). R FREQ is still required if an external clock
is used at SYNC/EN, and the SYNC/EN input frequency should be within ±30% of the
frequency set by R FREQ .
REF
GND
FB2
DRV2
SUP2
13
14
15
16
17
13
14
15
16
17
1.25V Reference Output. Connect a 0.1μF or larger ceramic capacitor (C9) from REF to GND.
Analog/Signal Ground
OUT2 Feedback Input. Connect a resistive-divider (R5, R6) from OUT2 to FB2 to GND to
regulate FB2 to 0.8V.
OUT2 Gate Drive. DRV2 connects to the gate of an external N-channel MOSFET to form a
positive linear voltage regulator.
Supply Input for DRV2. Connect to a voltage source of at least 1V above the maximum
desired DRV2 gate voltage.
12
______________________________________________________________________________________
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